1. Field of the Invention
The present invention generally relates to a method of forming a semiconductor device, and more particularly to a method of fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and SOI substrate on the same chip.
2. Description of the Related Art
Using merged dynamic random access memory (DRAM) and logic technology to fabricate a system on a semiconductor chip (e.g., so-called "system-on-chip" (SOC)) has many advantages including reduction of memory latency, larger bandwidth, high-speed processing, and cost reduction.
For deep submicron CMOS logic devices, it is advantageous to build the circuits on silicon on insulator (SOI) substrate to improve the performance. However, due to the buried oxide structure and processing techniques used to form an SOI substrate, many devices cannot be built easily on the SOI substrate. For example, a large capacitor on SOI will have a difficult time making contact to the ground node. As another example, the deep trench capacitor DRAM devices, which are typically built on a bulk silicon substrate, are very difficult to integrate into the SOI substrate, as the merged DRAM/logic technology. That is, the deep trench capacitor DRAM typically cannot be built on the SOI because of the oxide barrier of the SOI which makes trench processing very complicated.
Thus, as the logic technology migrates to silicon-on-insulator (SOI) substrate technology, it becomes difficult to fabricate a DRAM that requires deep trench capacitor structures, or having a large-sized capacitor.
Additionally, thermal dissipation is poor for devices built on the conventional SOI substrate. High temperature will cause great performance degradation.
Moreover, if analog and digital devices are built on a single substrate (e.g., bulk), then high frequency noise (interference) results from the mixed signals. That is, there is no separation of noise-sensitive and noise-insensitive devices and thus the signals output therefrom are subject to interference.